Start 01 April 2011
End 30 March 2014
Area: Design Methodologies for Embedded Systems
The PRESTO project aims at improving test-based embedded systems development and validation, while considering the constraints of industrial development processes. This project is based on the integration of :
(a) test traces exploitation (generated by test execution in the software integration phase induced by the industrial development process, to validate the requirements of the system) along with
(b) platform models and
(c) design space exploration techniques.
The expected result of the project is to establish functional and performance analysis and platform optimisation at early stage of the design development.
The approach of PRESTO is to model the software/hardware allocation, by the use of modelling frameworks, such as the UML profile for model-driven development of Real Time and Embedded Systems (MARTE). The analysis tools, among them timing analysis including Worst Case Execution Time (WCET) analysis, scheduling analysis and possibly more abstract system-level timing analysis techniques will receive as inputs on the one hand information from the performance modelling of the HW/SW-platform, and on the other hand behavioural information of the software design from tests results of the integration test execution.
Of particular novelty in PRESTO is the exploitation of traces for the exclusion of over-pessimistic assumptions during timing analysis: instead of taking all possible inputs and states into account for a worst-case analysis, a set of relevant traces is analyzed separately to reduce the set of possible inputs and states for each trace.
A particular attention will be given to industrial development constraints, which means:
1) as little cost as possible in term of extra specification time and need of expertise,
2) a simple use of the tools,
3) a smooth integration in the current design process,
4) a tool framework flexible enough to be adapted to different process methodologies, design languages and integration test frameworks,
5) analysis results validated by confrontation with real platform results, and platform modelling for fast prototyping improved from this confrontation.
L. Pomante. "System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems". IEEE International Conference on Application-specific Systems, Architectures and Processors, Santa Monica, Settembre 2011.
L. Pomante. "System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems". 2nd Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms (DITAM'2013, Poster), Berlino, Gennaio 2013.
L. Pomante, S. Marchesani, P. Serri. "Design Space Exploration for Heterogeneous Multi Multi-Core Processor Dedicated Systems". 3th Workshop on Design, Modeling and Evaluation of Cyber Physical Systems (CyPhy'13), Philadelphia, Aprile 2013.